1. Field of the Invention
The invention pertains to a method for circuitizing the inside of through-holes or other openings in an electronic circuit package such that the plated through-holes are personalized to permit multiple wires to pass through one drilled hole.
2. Description of the Related Art
A substrate, such as a printed circuit board substrate, is conventionally selectively metallized, e.g., an electrical circuit is formed on the substrate, by initially forming a patterned seeding layer of, for example, palladium (Pd) on a surface of the substrate. The resulting substrate is then immersed in a metal plating bath, such as an electroless copper plating bath, where the corresponding metal, e.g., copper, is selectively deposited from solution just onto the patterned seeding layer. The selectively deposited copper then constitutes the desired selective metallization, e.g., the desired electrical circuit.
When forming the patterned seeding layer, either a subtractive or an additive procedure is used. In the subtractive procedure, an unpatterned seeding layer of, for example, palladium is initially formed on the substrate surface of interest. This is achieved by, for example, sputtering the seed metal onto the substrate surface. Alternatively, the seed metal is deposited from solution. For example, an unpatterned layer of palladium is readily deposited onto the substrate surface from a solution containing a palladium salt and tin chloride. Once the seed metal is deposited, a layer of photoresist is deposited on the seeding layer, exposed through a mask bearing the pattern of interest and developed. The underlying seeding layer is then etched, e.g., chemically etched, while using the patterned photoresist as an etch mask. Thereafter, the photoresist is chemically stripped, leaving just the patterned seeding layer.
In the additive procedure, a layer of photoresist is initially deposited onto the substrate surface of interest, exposed through a mask and developed. A metal seed, such as palladium, is then deposited onto the substrate surface of interest, while using the patterned photoresist layer as a deposition mask. The patterned photoresist layer (as well as the metal seed deposited onto the photoresist, per se) is then chemically stripped, leaving just the metal seed deposited into the openings in the patterned photoresist layer, which constitutes the patterned seeding layer.
As is known, the use of photoresists and the corresponding chemical developers and strippers is environmentally undesirable. Consequently, attempts have been made to develop methods for forming patterned seeding layers which do not rely on the use of photoresists.
One method for forming a patterned seeding layer which does not rely on the use of a photoresist is described by Thomas H. Baum et al. in "Photoselective Catalysis of Electroless Copper Solutions for the Formation of Adherent Copper Films onto Polyimide," Chem. Mater., Vol. 3, No. 4, 1991, pp. 714-720. According to this journal article, a patterned seeding layer of palladium is formed on a surface of a polyimide substrate by immersing the substrate surface in an aqueous seeding solution. This solution includes hydrated forms of potassium trioxalatoferrate (K.sub.3 Fe (C.sub.2 O.sub.4).sub.3) and tetraamine palladium chloride (Pd(NH.sub.3).sub.4 Cl.sub.2). The resulting layer of seeding solution on the substrate surface is then irradiated with UV light through a mask, to photo-selectively deposit palladium metal from the UV-irradiated regions of the solution onto the substrate surface. As a result, a patterned palladium seeding layer is formed without the use of a photoresist. (This patterned seeding layer remains in contact with, and surrounded by, the unexposed regions of the layer of seeding solution.)
According to the Baum et al journal article, immersing a polyimide substrate bearing a patterned palladium seeding layer, produced as described above, in an electroless copper plating bath having a pH of 12 results in deposition of copper just onto the palladium. However, as discussed below, it has been found by the present inventors that subsequent immersion of a second, third, fourth, etc., such polyimide substrate into the same electroless copper plating bath quickly results in serious difficulties. Moreover, these very same difficulties arise when the above-described method of photoselective palladium deposition is applied to other organic substrates, such as the epoxy resin/fiberglass substrates and fluoropolymer-containing substrates used in printed circuit board manufacture. Further, these same difficulties arise when the above-described method of photoselective palladium deposition is applied to inorganic, ceramic substrates, such as alumina substrates, aluminum nitride substrates and silicon nitride substrates.
In addition to plating the surface of the printed circuit board, it also is often important to plate the various through-holes and vias that connect one layer of a multilayer circuit board to one or more other layers. The term "through-hole" is used to mean a hole that connects non-adjacent layers. The term "via" is used to mean a hole that connects adjacent layers. In this application the term "through-hole" is used collectively, to designate through-holes and vias.
Current printed circuit board manufacturing techniques employ the use of plated through-holes to make the connection from one layer to another within the same board. Typically, the holes are mechanically drilled, then seeded with appropriate catalyst such that a thin layer of electroless copper is deposited across the entire structure, including the interior of the drilled holes. The board would then be electrolytically plated with additional copper to the desired thickness. In subsequent processing steps, the external layers are personalized by way of subtractive etching of selected areas defined by the imaged photoresist. To prevent etching the plated copper within the through-holes, the photoresist covers (i.e., tents) the holes during this process. With such a process, a small wire (typically 6 mils in width) on one layer gains access to other layers through a large hole (typically 18 mils in diameter or more). Thus, whereas surface area is considered premium on the x-y planes of a circuit board, the z-direction (i.e., the through-holes) are not so well utilized (since typically only one wire is used per through-hole).